DPLS350E
Document number: DS31230 Rev. 4 - 2
1 of 5
www.diodes.com
April 2009
© Diodes Incorporated
DPLS350E
LOW V
CE(SAT)
PNP SURFACE MOUNT TRANSISTOR
Features
• Epitaxial Planar Die Construction
• Ideally Suited for Automated Assembly Processes
• Ideal for Medium Power Switching or Amplification Applications
• Lead Free By Design/RoHS Compliant (Note 1)
• "Green" Device (Note 2)
Mechanical Data
• Case: SOT-223
• Case Material: Molded Plastic, "Green” Molding Compound.
UL Flammability Classification Rating 94V-0
• Moisture Sensitivity: Level 1 per J-STD-020D
• Terminals: Finish — Matte Tin annealed over Copper leadframe
(Lead Free Plating). Solderable per MIL-STD-202, Method 208
• Marking Information: See Page 4
• Ordering Information: See Page 4
• Weight: 0.115 grams (approximate)
Maximum Ratings @T
A
= 25°C unless otherwise specified
Characteristic Symbol Value Unit
Collector-Base Voltage
V
CBO
-60 V
Collector-Emitter Voltage
V
CEO
-50 V
Emitter-Base Voltage
V
EBO
-6 V
Peak Pulse Current
I
CM
-5 A
Continuous Collector Current
I
C
-3 A
Base Current
I
B
-1 A
Thermal Characteristics
Characteristic Symbol Value Unit
Power Dissipation (Note 3) @ T
A
= 25°C P
D
1 W
Thermal Resistance, Junction to Ambient Air (Note 3) @ T
A
= 25°C
R
JA
125 °C/W
Operating and Storage Temperature Range
T
J
, T
STG
-55 to +150 °C
Notes: 1. No purposefully added lead.
2. Diodes Inc.'s "Green" policy can be found on our website at http://www.diodes.com/products/lead_free/index.php.
3. Device mounted on FR-4 PCB; pad layout as shown on page 4 or in Diodes Inc. suggested pad layout document AP02001, which can
be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.
Top View
Device Schematic
Pin Out Configuration
3
1
2,4
C
O
L
L
E
C
T
O
R
E
M
I
T
T
E
R
B
A
S
E
4
3
2
1
C
C
B
E
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