Diodes DMP58D0SV User Manual download pdf

DMP58D0SV

Document number: DS31293 Rev. 4 - 2

1 of 5

www.diodes.com

July 2009

DMP58D0SV

DUAL P-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR

Features

• Low On-Resistance

• ESD Protected Gate to 500V

• Low Input Capacitance

• Fast Switching Speed

• Lead Free By Design/RoHS Compliant (Note 3)

• “Green” Device (Note 4)

• Qualified to AEC-Q 101 Standards for High Reliability

Mechanical Data

• Case: SOT-563

• Case Material: Molded Plastic, "Green" Molding Compound.

UL Flammability Classification Rating 94V-0

• Moisture Sensitivity: Level 1 per J-STD-020D

• Terminals: Finish ⎯ Matte Tin annealed over Copper leadframe.

Solderable per MIL-STD-202, Method 208

• Terminal Connections: See Diagram

• Marking Information: See Page 3

• Ordering Information: See Page 3

• Weight: 0.006 grams (approximate)

Maximum Ratings @T

= 25°C unless otherwise specified

Characteristic Symbol Value Units

Drain-Source Voltage

DSS

-50 V

Drain-Gate Voltage (Note 1)

DGR

-50 V

Gate-Source Voltage Continuous

GSS

Drain Current (Note 2) Continuous

-160 mA

Thermal Characteristics @T

= 25°C unless otherwise specified

Characteristic Symbol Value Units

Total Power Dissipation (Note 2)

400 mW

Thermal Resistance, Junction to Ambient (Note 2)

313

°C/W

Operating and Storage Temperature Range

, T

STG

-55 to +150

°C

Electrical Characteristics @T

= 25°C unless otherwise specified

Characteristic Symbol Min Typ Max Unit Test Condition

OFF CHARACTERISTICS (Note 5)

Drain-Source Breakdown Voltage

DSS

-50

⎯ ⎯

= 0V, I

= -250μA

Zero Gate Voltage Drain Current

DSS

⎯ ⎯

-1

μA

= -50V, V

= 0V

Gate-Body Leakage

GSS

⎯ ⎯

±5 μA

= ±20V, V

= 0V

ON CHARACTERISTICS (Note 5)

Gate Threshold Voltage

(

)

-0.8

⎯

-2.1 V

= V

, I

= -250μA

Static Drain-Source On-Resistance

(

)

⎯

6 8

Ω V

= -5V, I

= -0.100A

Forward Transconductance

0.05

⎯ ⎯

= -25V, I

= -0.1A

DYNAMIC CHARACTERISTICS

Input Capacitance

iss

⎯

= -25V, V

= 0V, f = 1.0MHz

Output Capacitance

oss

⎯

Reverse Transfer Capacitance

rss

⎯

1.4

⎯

Notes: 1. R

≤ 20KΩ.

2. Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch; pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which

can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.

3. No purposefully added lead.

4. Diodes Inc’s “Green” policy can be found on our website at http://www.diodes.com/products/lead_free/index.php.

5. Short duration pulse test used to minimize self-heating effect.

SOT-563

TOP VIEW

Internal Schematic

TOP VIEW

ESD protected to 500V

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DMP58D0SV 1

Summary of Contents

Page 1 - DMP58D0SV

DMP58D0SV Document number: DS31293 Rev. 4 - 2 1 of 5 www.diodes.com July 2009© Diodes Incorporated DMP58D0SV DUAL P-CHANNEL ENHANCEMENT MODE FIELD

Page 2

DMP58D0SV Document number: DS31293 Rev. 4 - 2 2 of 5 www.diodes.com July 2009© Diodes Incorporated DMP58D0SV Fig. 1 Typical Output Characteristi

Page 3

DMP58D0SV Document number: DS31293 Rev. 4 - 2 3 of 5 www.diodes.com July 2009© Diodes Incorporated DMP58D0SV Fig. 7 Gate Threshold Variation vs.

DMP58D0SV Document number: DS31293 Rev. 4 - 2 4 of 5 www.diodes.com July 2009© Diodes Incorporated DMP58D0SV Package Outline Dimensions

Page 5

DMP58D0SV Document number: DS31293 Rev. 4 - 2 5 of 5 www.diodes.com July 2009© Diodes Incorporated DMP58D0SV IMPORTANT NOTICE DIODES INCORPORA

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